This application relates to a field programmable radio frequency communications systems and more particularly to field programmable memory arrangement for controlling the movement of multi bit communications data into and out of memory.
Descriptions of the various components of the system are contained in co-pending patent applications owned by the assignee hereof and filed concurrently herewith, specifically: U.S. Pat. No. 6,091,765, Issued on Jul. 18, 2000, entitled xe2x80x9cReconfigurable Radio System Architecture And Method Thereforxe2x80x9d; U.S. patent application Ser. No. 09/184,716, entitled xe2x80x9cConfigurable Circuits for Field Programmable Radio Frequency Communications Equipment and Methods Thereforxe2x80x9d; U.S. patent application Ser. No. 09/184,940, entitled xe2x80x9cA System For Accelerating the Reconfiguration of a Transceiver and Method Thereforxe2x80x9d; U.S. patent application Ser. No. 09/184,710, entitled xe2x80x9cA Field Programmable Radio Frequency Communications Equipment Including A Configurable IF Circuit, And Method Thereforexe2x80x9d; U.S. patent application Ser. No. 09/184,709, entitled xe2x80x9cA Field Programmable Modulator-Demodulator Arrangement For Radio Frequency Communications Equipment, And Method Thereforxe2x80x9d; U.S. patent application Ser. No. 09/184,711, entitled xe2x80x9cA Digital Noise Blanker For Communications Systems And Methods Thereforxe2x80x9d; U.S. patent application Ser. No. 09/184,708, entitledxe2x80x9d TCM Revisiting System and Methodxe2x80x9d; U.S. patent application Ser. No. 09/184,712, entitled xe2x80x9cLeast Squares Phase Fit As Frequency Estimatexe2x80x9d; U.S. patent application Ser. No. 09/184,941, entitled xe2x80x9cPolar Computation of Branch Metrics For TCMxe2x80x9d; U.S. patent application Ser. No. 09/184,715, entitled xe2x80x9cEfficient Modified Viterbi Decoderxe2x80x9d; U.S. patent application Ser. No. 09/184,713, entitled xe2x80x9cReceiver For a Reconfigurable Radio System and Method Thereforexe2x80x9d; each of which is incorporated herein by reference.
In the use of radio frequency equipment for communications, there is a need for a large variety of communication devices, such as receivers, transmitters and transceivers that are able to operate with a large variety of communications schemes, or waveforms such as, AM, AME, A3E, H3E, J3E, CW, SSB, M-PSK, QAM, ASK, angular modulation, including FM, PM, FSK, CMP, MSK, CPFSK etc., as well as a need of being able to process the signals within the communications devices, such as by filtering, gain control, impulse noise rejection, signal format conversion, re-sampling, etc. To achieve this in the past, a plurality of different dedicated pieces of equipment was required, such as, receivers, transmitters and transceivers, each designed to operate with separate communication schemes or waveforms, or a limited group of schemes or waveforms. Hence it would be desirous to have a configurable type of radio frequency communications equipment that is readily field programmable to function as a transmitter and receiver and to be able to be programmed to function with any of the above mentioned communications schemes or waveforms.
An important building block for a configurable type transceiver is a configurable digital intermediate frequency (IF) transmitter and receiver signal processing circuit that can be field programmed to provide the receiver demodulation functions and transmitter modulator functions and also corresponding waveform filtering and shaping. The output signals of the configurable IF signal processor often require further conditioning and demodulation. Depending upon its configuration, such configurable digital IF processor is required to provide a variety of types of output signals that involve various selective processes such as filtering, format conversion, re-sampling etc., and therefor different types of signal streams are outputted, which may be made of several streams of small effective depth or fewer (even one) streams of large effective depth. The output may include signals having real and quadature portions, magnitude and phase portions, real portions, or output signals that have several different sample rates (such as single side band).
The output circuit for such digital processing systems usually takes the form of a first in first out (FIFO) register or memory arrangement in which the output signals are generally stored in the register in a time of receipt sequence, in which output signals from different sources are interleaved. The interleaving of signals from different sources imposes unnecessary overhead requirements on any subsequent circuits attempting to further condition the output signals, since the signals must be read, de-interleaved, and stored before any additional processing of the output signals takes place. Multiple FOFOs could be used, one of each type of output signal required for each type of signaling scheme, however, the FIOFs would not be subject to efficient use in that in some signaling schemes, such as FM, would only use one FIFO, while the others would remain idle and it would be difficult to take advantage of the idle storage purposes.
It therefor would be desirable if only a single FIFO could be employed that can handle the variety of output signals for all the signaling schemes to be configured. It would also be desirable if the single FIFO could input and output multiple digital signals from a single source. It would also be desirable if an arrangement would be provided to function with the single FIFO that would identify the source of the signals, and further process and store the signals according to the various configured signaling schemes and time sequence.
Is therefor an object of this invention to provide a new and improved memory arrangement that can process the inputting and outputting of digital signals from different sources that correspond any selected one of a plurality of communications schemes or waveforms.
It is also an object of this invention to provide a new and improved memory arrangement that can employ a single FIFO which can support the inputting and outputting of data streams comprised of multiple streams with small effective depth as well as data streams comprised of fewer streams of larger effective depth corresponding to any of a selected one of a plurality of communications schemes or waveforms.
It is also an object of this invention to provide a new and improved memory arrangement that can employ a single FIFO which can support the simultaneous inputting and outputting of multiple data streams from the same source corresponding to any of a plurality of selected communications schemes or waveforms.
Is also an object of this invention to provide a new and improved circuit for receiving output signals from a FIFO and rearranging the signals from the FIOF in accordance with source and timing corresponding to any of a plurality of selected communications schemes or waveforms.
Is also an object of this invention to provide a new and improved circuit for outputting signals corresponding to any of a plurality of selected communications schemes or waveforms either directly from the FIFO or that have been re-arranged accordance with signal source and timing.
Is also an object of this invention to provide a new and improved circuit for storing in memory signals corresponding to any of a plurality of selected communications schemes or waveforms by interleaving the signal bit-level representations in dedicated memory address assembly blocks of data in a timing sequence for improving the ease of processing the data.